//-----------------------------------------顶层
module all_top
(
input refclk,
input rst_n,
input in_top,
output vs,
output hs,
output [4:0]r,
output [5:0]g,
output [4:0]b,
output out_tx
);
wire uart_clk;
wire uart_rst;
wire clk_vga;
wire rst_vga;
pll//=============VGA 40m时钟
pll_inst
(
.areset ( ~rst_n ),
.inclk0 ( refclk ),
.c0 ( clk_vga ),
.locked ( rst_vga )
);
pll_5mpll_5m_inst //-----------uart 5m时钟
(
.areset ( ~rst_n ),
.inclk0 ( refclk ),
.c0 ( uart_clk ),
.locked ( uart_rst )
);

wire [7:0]out_top;
wire out_stop;
uart_top
uart_top_inst//=====uart_rx
(
.clk(uart_clk),
.rst(uart_rst),
.in_top(in_top),
.out_top(out_top),
.out_stop(out_stop)
);
uart_tx
uart_tx_inst
(
.clk(uart_clk),
.rst(uart_rst),
.in_rx(out_top),
.in_stop(out_stop),
.out_tx(out_tx)
);
wire [7:0]ym_out;
wire ym_en;
yima//-------------文件发送以ASCII，所以要译码
yima_inst
(
.clk(uart_clk),
.rst(uart_rst),
.in_top(out_top),
.in_stop(out_stop),
.ym_out(ym_out),
.ym_en(ym_en)
);
wire [11:0]st_cont;
wire st_en;
st_m//-------------协议
st_m_inst
(
.clk(uart_clk),
.rst(uart_rst),
.in(ym_out),
.in_stop1(ym_en),
.st_enr(st_enr),
.st_eng(st_eng),
.st_enb(st_enb),
.st_cont(st_cont)
);

wire [12:0]add_r;
wire [9:0]cont_v;
wire [10:0]cont_h;
rden//-----------rom读使能，读地址
rden_inst
(
.clk(clk_vga),
.rst(rst_vga),
.en(en),
.cont_v(cont_v),
.cont_h(cont_h),
.st_cont(st_cont),
.rdadd(add_r),
.rden(rden)
);
wire [7:0]q,q2;
wire [7:0]q1;
ramramr_inst (//---------存r
.data ( ym_out ),
.rdaddress ( add_r ),
.rdclock ( clk_vga ),
.rden ( rden ),
.wraddress ( st_cont ),
.wrclock ( uart_clk ),
.wren ( st_enr ),
.q ( q )
);
ramramg_inst (//------存G
.data ( ym_out ),
.rdaddress ( add_r ),
.rdclock ( clk_vga ),
.rden ( rden ),
.wraddress ( st_cont ),
.wrclock ( uart_clk ),
.wren ( st_eng ),
.q ( q1 )
);
ramramb_inst (//---------存b
.data ( ym_out ),
.rdaddress ( add_r ),
.rdclock ( clk_vga ),
.rden ( rden ),
.wraddress ( st_cont ),
.wrclock ( uart_clk ),
.wren ( st_enb ),
.q ( q2)
);

VGA_top
VGA_top_inst
(
.clk(clk_vga),
.rst(rst_vga),
.in_top(q),
.in_top1(q1),
.in_top2(q2),
.vs(vs),
.hs(hs),
.r(r),
.g(g),
.b(b),
.en(en),
.cont_h(cont_h),
.cont_v(cont_v)
);

endmodule


//-----------------------------------------------------------------------------------
module uart_top
(
input clk,
input rst,
input in_top,
output [7:0]out_top,
output out_stop
);
pd
pd_inst
(
.clk(clk),
.rst(rst),
.in_top(in_top),
.out_pd_starte(out_pd_starte)
);
ztj
ztj_inst
(
.clk(clk),
.rst(rst),
.in_top_z(in_top),
.in_en(out_pd_starte),
.out_stop(out_stop),
.out_ztj(out_top)
);
endmodule

module pd
(
input clk,
input rst,
input in_top,
output out_pd_starte
);
reg vs_pd11;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_pd11<=1'b0;
else
vs_pd11<=in_top;
end
reg vs_pd22;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_pd22<=1'b0;
else
vs_pd22<=vs_pd11;
end
reg vs_pd;
wire neg;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_pd<=1'b0;
else
vs_pd<=vs_pd22;
end
assign neg=(~vs_pd22)&vs_pd;
//----------------------------------
reg vs_pd1;
reg [9:0]cont;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont<=1'b0;
else if(cont==10'd174)//9*PI
cont<=1'b0;
else if(vs_pd1==1'b1)
cont<=cont+1'b1;
end


always@(posedge clk )
begin
if(~rst)
vs_pd1 <=1'b0;
else if(neg==1'b1)
vs_pd1 <=1'b1;
else if(cont==10'd174)
vs_pd1<=1'b0;
end

reg vs_pd2;
always@(posedge clk )
begin
if(~rst)
vs_pd2 <=1'b0;
else if(vs_pd1 ==1'b1)
vs_pd2 <=1'b0;
else
vs_pd2<=neg;
end
assign out_pd_starte=vs_pd2;
endmodule

module ztj
(
input clk,
input rst,
input in_top_z,
input in_en,
output [7:0]out_ztj,
output out_stop
);
parameter IDLE=4'b0000;
parameter start=4'b0001;
parameter bit0=4'b0010;
parameter bit1=4'b0011;
parameter bit2=4'b0100;
parameter bit3=4'b0101;
parameter bit4=4'b0110;
parameter bit5=4'b0111;
parameter bit6=4'b1000;
parameter bit7=4'b1001;
parameter stop=4'b1010;

parameter PI=19-1; //39-1
reg vs;
reg [9:0]cont1;
always@(posedge clk)
begin
if(~rst)
vs<=1'b0;
else if(in_en==1'b1)
vs<=1'b1;
else if(cont1==10*(PI+1))
vs<=1'b0;
end

always@(posedge clk)
begin
if(~rst)
cont1<=10'd0;
else if(vs==1'b1)
cont1<=cont1+10'd1;
else
cont1<=10'd0;
end

reg [6:0]cont;
always@(posedge clk)
begin
if(~rst)
cont<=7'd0;
else if(cont==PI)
cont<=7'd0;
else if(vs==1'b1)
cont<=cont+7'd1;
else
cont<=7'd0;
end
reg [3:0]cont_z;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont_z<=4'd0;
else if(vs==1'b0)
cont_z<=4'd0;
else if((cont_z==4'd10)&&(cont==PI))
cont_z<=4'd0;
else if(cont==PI)
cont_z<=cont_z+4'd1;
end
//----------------------------------------------
reg [7:0]out; //
reg [3:0]current_state;
reg [3:0]next_state;
always@(posedge clk or negedge rst)
begin
if(~rst)
current_state<=IDLE;
else
current_state<=next_state;
end
always@(*)
begin
next_state=IDLE;
case(current_state)
IDLE:if(in_en==1'b1)
next_state=start;
else
next_state=IDLE;
start:if(cont_z==4'd1)
next_state=bit0;
else
next_state=start;
bit0:if(cont_z==4'd2)
next_state=bit1;
else
next_state=bit0;
bit1:if(cont_z==4'd3)
next_state=bit2;
else
next_state=bit1;
bit2:if(cont_z==4'd4)
next_state=bit3;
else
next_state=bit2;
bit3:if(cont_z==4'd5)
next_state=bit4;
else
next_state=bit3;
bit4:if(cont_z==4'd6)
next_state=bit5;
else
next_state=bit4;
bit5:if(cont_z==4'd7)
next_state=bit6;
else
next_state=bit5;
bit6:if(cont_z==4'd8)
next_state=bit7;
else
next_state=bit6;
bit7:if(cont_z==4'd9)
next_state=stop;
else
next_state=bit7;
stop:if(cont_z==4'd10||vs==1'b0)
next_state=IDLE;
else
next_state=stop;
default:next_state=IDLE;
endcase
end
//-------------------------------------------
reg vs_stop;
always@(posedge clk)
begin
if(~rst)
vs_stop<=1'b0;
else if((cont==(PI+1)/2-1)&&(current_state==stop))
vs_stop<=1'b1;
else
vs_stop<=1'b0;
end
assign out_stop=vs_stop;
//-------------------------------------------
reg vs_cont;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_cont<=1'b0;
else if(cont==(PI+1)/2-1)
vs_cont<=1'b1;
else
vs_cont<=1'b0;
end
//----------------------------------------
reg vs_tb1;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_tb1<=1'b0;
else
vs_tb1<=in_top_z;
end
reg vs_tb2;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_tb2<=1'b0;
else
vs_tb2<=vs_tb1;
end
reg vs_tb;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_tb<=1'b0;
else
vs_tb<=vs_tb2;
end
//---------------------------------------
always@(*)
begin
if(~rst)
out=8'b0;
else
case(current_state)
IDLE:if(in_en==1'b1)
out=0;
else
out=out;
start:
out=out;
bit0:if(vs_cont==1'b1)
out[0]=vs_tb;
else
out[0]=out[0];

bit1:if(vs_cont==1'b1)
out[1]=vs_tb;
else
out[1]=out[1];

bit2:if(vs_cont==1'b1)
out[2]=vs_tb;
else
out[2]=out[2];

bit3:if(vs_cont==1'b1)
out[3]=vs_tb;
else
out[3]=out[3];

bit4:if(vs_cont==1'b1)
out[4]=vs_tb;
else
out[4]=out[4];

bit5:if(vs_cont==1'b1)
out[5]=vs_tb;
else
out[5]=out[5];

bit6:if(vs_cont==1'b1)
out[6]=vs_tb;
else
out[6]=out[6];

bit7:if(vs_cont==1'b1)
out[7]=vs_tb;
else
out[7]=out[7];

default:out=out;
endcase
end
reg [7:0]out1;
always@(posedge clk or negedge rst)
begin
if(~rst)
out1<=8'd0;
else if(vs_stop==1'b1)
out1<=out;
else
out1<=out1;
end

assign out_ztj=out1;
endmodule

module uart_tx
(
input clk,
input rst,
input [7:0]in_rx,
input in_stop,
output out_tx
);

ztj_tx
ztj_tx_inst
(
.clk(clk),
.rst(rst),
.in(in_rx),
.tx_en(in_stop),
.out_tx(out_tx)
);
endmodule


module ztj_tx
(
input clk,
input rst,
input [7:0]in,
input tx_en,
output out_tx
);
parameter IDLE=4'b0000;
parameter start=4'b0001;
parameter bit0=4'b0010;
parameter bit1=4'b0011;
parameter bit2=4'b0100;
parameter bit3=4'b0101;
parameter bit4=4'b0110;
parameter bit5=4'b0111;
parameter bit6=4'b1000;
parameter bit7=4'b1001;
parameter stop=4'b1010;

parameter PI=19-1;
reg vs;
reg [9:0]cont1;
always@(posedge clk)
begin
if(~rst)
vs<=1'b0;
else if(tx_en==1'b1)
vs<=1'b1;
else if(cont1==10*(PI+1))
vs<=1'b0;
end

always@(posedge clk)
begin
if(~rst)
cont1<=10'd0;
else if(vs==1'b1)
cont1<=cont1+10'd1;
else
cont1<=10'd0;
end

reg [6:0]cont;
always@(posedge clk)
begin
if(~rst)
cont<=7'd0;
else if(cont==PI)
cont<=7'd0;
else if(vs==1'b1)
cont<=cont+7'd1;
else
cont<=7'd0;
end

reg [3:0]cont_z;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont_z<=4'd0;
else if(vs==1'b0)
cont_z<=4'd0;
else if((cont_z==4'd10)&&(cont==PI))
cont_z<=4'd0;
else if(cont==PI)
cont_z<=cont_z+4'd1;
end
//----------------------------------------------
reg out_ztj;
reg [3:0]current_state;
reg [3:0]next_state;
always@(posedge clk or negedge rst)
begin
if(~rst)
current_state<=IDLE;
else
current_state<=next_state;
end
always@(*)
begin
next_state=IDLE;
case(current_state)
IDLE:if(tx_en==1'b1)
next_state=start;
start:if(cont_z==4'd1)
next_state=bit0;
else
next_state=start;
bit0:if(cont_z==4'd2)
next_state=bit1;
else
next_state=bit0;
bit1:if(cont_z==4'd3)
next_state=bit2;
else
next_state=bit1;
bit2:if(cont_z==4'd4)
next_state=bit3;
else
next_state=bit2;
bit3:if(cont_z==4'd5)
next_state=bit4;
else
next_state=bit3;
bit4:if(cont_z==4'd6)
next_state=bit5;
else
next_state=bit4;
bit5:if(cont_z==4'd7)
next_state=bit6;
else
next_state=bit5;
bit6:if(cont_z==4'd8)
next_state=bit7;
else
next_state=bit6;
bit7:if(cont_z==4'd9)
next_state=stop;
else
next_state=bit7;
stop:if(cont_z==4'd10||vs==1'b0)
next_state=IDLE;
else
next_state=stop;
default:next_state=IDLE;
endcase
end

//-------------------------------------------
always@(posedge clk or negedge rst)
begin
if(~rst)
out_ztj<=1'b1;
else
case(current_state)
IDLE:
out_ztj<=1'b1;
start:
out_ztj<=1'b0;
bit0:
out_ztj<=in[0];
bit1:
out_ztj<=in[1];
bit2:
out_ztj<=in[2];
bit3:
out_ztj<=in[3];
bit4:
out_ztj<=in[4];
bit5:
out_ztj<=in[5];
bit6:
out_ztj<=in[6];
bit7:
out_ztj<=in[7];
stop:
out_ztj<=1'b1;
default:out_ztj<=1'b1;
endcase
end
assign out_tx=out_ztj;
endmodule

//--------------------------------------------------------------
module yima
(
input clk,
input rst,
input [7:0]in_top,
input in_stop,
output [7:0]ym_out,
output ym_en
);
reg [3:0]ym;
always@(posedge clk or negedge rst)
begin
if(~rst)
ym<=4'h0;
else
case(in_top)
8'h30:ym<=4'h0;
8'h31:ym<=4'h1;
8'h32:ym<=4'h2;
8'h33:ym<=4'h3;
8'h34:ym<=4'h4;
8'h35:ym<=4'h5;
8'h36:ym<=4'h6;
8'h37:ym<=4'h7;
8'h38:ym<=4'h8;
8'h39:ym<=4'h9;
//--------------
8'h41:ym<=4'hA;
8'h42:ym<=4'hB;
8'h43:ym<=4'hC;
8'h44:ym<=4'hD;
8'h45:ym<=4'hE;
8'h46:ym<=4'hF;
//-------------
8'h61:ym<=4'ha;
8'h62:ym<=4'hb;
8'h63:ym<=4'hc;
8'h64:ym<=4'hd;
8'h65:ym<=4'he;
8'h66:ym<=4'hf;
default:ym<=ym;
endcase
end
reg [1:0]cont;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont<=2'd0;
else if(cont==2'd1&&in_stop==1'b1)
cont<=2'd0;
else if(in_stop==1'b1)
cont<=cont+1'b1;
end

reg [7:0]a3;
always@(posedge clk or negedge rst)
begin
if(~rst)
a3<=7'd0;
else if(cont==2'b0&&in_stop==1'b1)
a3[7:4]<=ym;
else if(cont==2'd1&&in_stop==1'b1)
a3[3:0]<=ym;
end
reg vs;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs<=1'b0;
else if(cont==2'd1&&in_stop==1'b1)
vs<=1'b1;
else
vs<=1'b0;
end
assign ym_out=a3;
assign ym_en=vs;
endmodule

//-------------------------------------------------------
module st_m
(
input clk,
input rst,
input [7:0]in,
input in_stop1,
output st_enr,
output st_eng,
output st_enb,
output [11:0]st_cont
);
parameter IDLE=4'b0000;
parameter S01=4'b0001;
parameter S02=4'b0010;
parameter S03=4'b0011;
parameter S04=4'b0100;
parameter LEN_LOW=4'b0101;
parameter LEN_HIG=4'b0110;
parameter DATA=https://www.it610.com/article/4'b0111;
reg in_stop;
always@(posedge clk or negedge rst)
begin
if(~rst)
in_stop<=1'b0;
else
in_stop<=in_stop1;
end
reg [3:0]current_state;
reg [3:0]next_state;
reg [11:0]LEN;
reg [11:0]N_cont;
reg st_en1;
reg st_en2;
reg st_en3;
always@(posedge clk or negedge rst)
begin
if(~rst)
current_state<=IDLE;
else
current_state<=next_state;
end
always@(*)
begin
next_state=IDLE;
case(current_state)
IDLE:if(in==8'h01&&in_stop==1'b1)
next_state=S01;
else
next_state=IDLE;
S01:if(in==8'h02&&in_stop==1'b1)
next_state=S02;
else if(in!=8'h02&&in_stop==1'b1)
next_state=IDLE;
else
next_state=S01;
S02:if(in==8'h03&&in_stop==1'b1)
next_state=S03;
else if(in!=8'h03&&in_stop==1'b1)
next_state=IDLE;
else
next_state=S02;
S03:if(in==8'h04&&in_stop==1'b1)
next_state=S04;
else if(in!=8'h04&&in_stop==1'b1)
next_state=IDLE;
else
next_state=S03;
S04:if(in_stop==1'b1)
next_state=LEN_LOW;
else
next_state=S04;
LEN_LOW:if(in_stop==1'b1)
next_state=LEN_HIG;
else
next_state=LEN_LOW;
LEN_HIG:if(in_stop==1'b1)
next_state=DATA;
else
next_state=LEN_HIG;
DATA:if(N_cont1==LEN&&in_stop==1'b1)
next_state=IDLE;
else
next_state=DATA;

default:next_state=IDLE;
endcase
end

always@(posedge clk or negedge rst)
begin
if(~rst)
LEN<=14'd0;
else if(next_state==LEN_LOW)
LEN[11:8]<=in[3:0];
else if(next_state==LEN_HIG&&in_stop==1'b1)
LEN[7:0]<=in;
else if(next_state==DATA)
LEN<=LEN;
else if(next_state==IDLE)
LEN<=14'd0;
end

always@(posedge clk or negedge rst)
begin
if(~rst)
N_cont<=12'd0;
else if( next_state == IDLE )
N_cont<=12'd0;
else if(next_state==DATA&&in_stop==1'b1)
N_cont<=N_cont+1'b1;
end
reg [11:0]N_cont1;
always@(posedge clk or negedge rst)
begin
if(~rst)
N_cont1<=12'd0;
else
N_cont1<=N_cont;
end

always@(posedge clk or negedge rst)
begin
if(~rst)
begin
st_en1<=1'b0;
st_en2<=1'b0;
st_en3<=1'b0;
end
else if(next_state==LEN_LOW)
begin
if(in[5:4]==2'b00)
st_en1<=1'b1;
else if(in[5:4]==2'b01)
st_en2<=1'b1;
else if(in[5:4]==2'b11)
st_en3<=1'b1;
end
else if( next_state == IDLE )
begin
st_en1<=1'b0;
st_en2<=1'b0;
st_en3<=1'b0;
end
end
//==========================================
reg st_en01,st_en02,st_en03;
always@(posedge clk or negedge rst)
begin
if(~rst)
begin
st_en01<=1'b0;
st_en02<=1'b0;
st_en03<=1'b0;
end
else if(st_en1==1'b1&&in_stop==1'b1)
st_en01<=1'b1;
else if(st_en2==1'b1&&in_stop==1'b1)
st_en02<=1'b1;
else if(st_en3==1'b1&&in_stop==1'b1)
st_en03<=1'b1;
else
begin
st_en01<=1'b0;
st_en02<=1'b0;
st_en03<=1'b0;
end
end

assign st_enr=st_en01;
assign st_eng=st_en02;
assign st_enb=st_en03;
assign st_cont=N_cont1;
endmodule
//---------------------------------------------------
module rden
(
input clk,
input rst,
input en,
input [9:0]cont_v,
input [10:0]cont_h,
input [11:0]st_cont,
output [12:0]rdadd,
output rden
);
//--------------------------------------rd
reg wr_stop;
always@(posedge clk or negedge rst)
begin
if(~rst)
wr_stop<=1'b0;
else if(st_cont==12'd4095)
wr_stop<=1'b1;
else
wr_stop<=1'b0;
end
reg [12:0]cont;
reg en1;
always@(posedge clk or negedge rst)
begin
if(~rst)
en1<=1'b0;
else
begin
if((((11'd215en1<=1'b1;
else
en1<=1'b0;
end
end
always@(posedge clk or negedge rst)
begin
if(~rst)
cont<=13'd0;
else
begin
if(cont==13'd4095)
cont<=13'd0;
else if(en1==1'b1)
cont<=cont+1'b1;
end
end
assign rdadd=cont;
assign rden=en1;
endmodule

/---------------------------------------------------
module VGA_top
(
input clk,
input rst,
input [7:0]in_top,
input [7:0]in_top1,
input [7:0]in_top2,
output vs,
output hs,
output [4:0]r,
output [5:0]g,
output [4:0]b,
output en,
output [9:0]cont_v,
output [10:0]cont_h
);
【FPGA|FPGA uart发送数据FPGA接收传送到VGA显示到屏幕（血的教训---端口接收数据时用三个寄存器消抖）】vga
vga_inst
(
.clk(clk),
.rst(rst),
.en(en),
.vga_vs(vs),
.vga_hs(hs),
.cont_v(cont_v),
.cont_h(cont_h)
);
rgb
rgb_inst
(
.clk(clk),
.rst(rst),
.en(en),
.cont_v(cont_v),
.cont_h(cont_h),
.in_top(in_top),
.in_top1(in_top1),
.in_top2(in_top2),
.r(r),
.g(g),
.b(b)
);

endmodule

module vga
(
input clk,
input rst,
output en,
output vga_vs,
output vga_hs,
output [9:0]cont_v,
output [10:0]cont_h
);
reg [10:0]cont_hs;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont_hs<=11'd0;
else if(cont_hs==11'd1055)
cont_hs<=11'd0;
else
cont_hs<=cont_hs+1'b1;
end
reg [9:0]cont_vs;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont_vs<=10'd0;
else if(cont_hs==11'd1055)
begin
if(cont_vs==10'd627)
cont_vs<=10'd0;
else
cont_vs<=cont_vs+1'b1;
end
end
assign cont_v=cont_vs;
assign cont_h=cont_hs;
reg vga_vs1; //行同步
always@(posedge clk or negedge rst)
begin
if(~rst)
vga_vs1<=1'b0;
else if(cont_vs==10'd0)
vga_vs1<=1'b1;
else if(cont_vs==10'd3)
vga_vs1<=1'b0;
end
assign vga_vs=~vga_vs1;
reg vga_hs1; //列同步
always@(posedge clk or negedge rst)
begin
if(~rst)
vga_hs1<=1'b0;
else if(cont_hs==11'd0)
vga_hs1=1'b1;
else if(cont_hs==11'd128)
vga_hs1<=1'b0;
end
assign vga_hs=vga_hs1;
//--------------------------------
reg en_vs;
always@(posedge clk or negedge rst)
begin
if(~rst)
en_vs<=1'b0;
else if(cont_vs==10'd26)
en_vs<=1'b1;
else if(cont_vs==10'd626)
en_vs<=1'b0;
end
reg en_hs;
always@(posedge clk or negedge rst)
begin
if(~rst)
en_hs<=1'b0;
else if(cont_hs==11'd215)
en_hs<=1'b1;
else if(cont_hs==11'd1015)
en_hs<=1'b0;
end
reg en1;
always@(posedge clk or negedge rst)
begin
if(~rst)
en1<=1'b0;
else if((en_vs==1'b1)&&(en_hs==1'b1))
en1<=1'b1;
else
en1<=1'b0;
end
assign en=en1;
endmodule


module rgb
(
input clk,
input rst,
input en,
input [9:0]cont_v,
input [10:0]cont_h,
input [7:0]in_top,
input [7:0]in_top1,
input [7:0]in_top2,
output [4:0]r,
output [5:0]g,
output [4:0]b
);
reg [4:0]rgb_r;
reg [5:0]rgb_g;
reg [4:0]rgb_b;
always@(posedge clk or negedge rst)
begin
if(~rst)
begin
rgb_r<=5'b00000;
rgb_g<=6'b000000;
rgb_b<=5'b00000;
end
else if(en==1'b1)
begin
if(((11'd215begin
rgb_r<=in_top[7:3];
rgb_g<=in_top1[7:2];
rgb_b<=in_top2[7:3];
end
else
begin
rgb_r<=5'b00000;
rgb_g<=6'b000000;
rgb_b<=5'b00000;
end


end
else
begin
rgb_r<=5'b00000;
rgb_g<=6'b000000;
rgb_b<=5'b00000;
end
end
assign r=rgb_r;
assign g=rgb_g;
assign b=rgb_b;
endmodule

推荐阅读

• 

  开机一直转圈
• 

  2月20日台州玉环清港镇卫生院九价预约条件一览
• 

  电商是什么 什么是电商商机，商机好项目
• 

  南昌地铁规划 以后南昌也有地铁啦
• 

  手机|华为P50确认全球发布，并带来全新影像技术，超越自己
• 

  游戏开发游戏运营内容，游戏开发运营公司的流程场景描述
• 

  mongodb如何修改密码 mongodb 密码连接
• 

  教育者谬误手册心得体会
• 

  如何处理债权人不同意债务转让的情况？
• 

  为患者做雾化 怎么样雾化
• 

  坐高铁可以带黄酒上高铁吗 坐高铁可以带黄酒吗?
• 

  八个字的生日祝福语有哪些？
• 

  安卓淘宝手机客户端,淘宝客户端下载安装步骤一文看懂
• 

  西山有什么风景 西山有哪些
• 

  ie80s
• 

  带云的诗句 关于云的诗句
• 

  翡翠手串的寓意 翡翠手串的寓意介绍
• 

  槐鹅是什么样子，和大白鹅有什么区别
• 

  核酸检测阴性怎么还是黄码
• 

  蚂蚁庄园登山赛怎么找不到 蚂蚁庄园登山赛在哪里入口

• python学习之|python学习之 实现QQ自动发送消息
• Quartz|Quartz 源码解析(四) —— QuartzScheduler和Listener事件监听
• FPGA|DDR3原理总结
• UI（三十）发送请求NSURLSession
• Fescar|Fescar example解析 - TM发送逻辑
• Android-发送通知/含Android8.0+耐心照着官方教程实现，不是很难
• 借助android|借助android uiautomator+情迁工具箱自动朗读实现语音红包自动发送语音,自动领取
• python获取linux系统信息，并发送邮件
• RocketMQ学习六-消息发送错误与解决方案
• RocketMQ学习四-消息发送高可用设计