Verilog专题（三十七）DEBUG专题 HDLBits_Verilog

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题目一（MUX）

module top_module (input sel,input [7:0] a,input [7:0] b,output out);?assign out = (~sel & a) | (sel & b);?endmodule?

我的修正（一）

module top_module (input sel,input [7:0] a,input [7:0] b,output [7:0]out);??assign out = sel?a:b;??endmodule

题目二（NAND） This three-input NAND gate doesn't work. Fix the bug(s).
You must use the provided 5-input AND gate:

module andgate ( output out, input a, input b, input c, input d, input e );

module top_module (input a, input b, input c, output out); //?andgate inst1 ( a, b, c, out );?endmodule

我的修正（二）

module top_module (input a, input b, input c, output out); //wire out1;andgate inst1 ( out1, a, b, c,1,1 );assign out = !out1;endmodule?

题目三（MUX） This 4-to-1 multiplexer doesn't work. Fix the bug(s).
You are provided with a bug-free 2-to-1 multiplexer:
module mux2 (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);

module top_module (input [1:0] sel,input [7:0] a,input [7:0] b,input [7:0] c,input [7:0] d,output [7:0] out); //?wire mux0, mux1;mux2 mux0 ( sel[0],a,b, mux0 );mux2 mux1 ( sel[1],c,d, mux1 );mux2 mux2 ( sel[1], mux0, mux1,out );?endmodule??

我的修正（三）

module top_module (input [1:0] sel,input [7:0] a,input [7:0] b,input [7:0] c,input [7:0] d,output [7:0] out); //?wire[7:0] mux00, mux11;mux2 mux0 ( sel[0], a, b, mux00 );mux2 mux1 ( sel[1]&sel[0], c, d, mux11 );mux2 mux21 ( sel[1], mux00, mux11, out );?endmodule?

题目四（Add/Sub） The following adder-subtractor with zero flag doesn't work. Fix the bug(s).

// synthesis verilog_input_version verilog_2001module top_module ( input do_sub,input [7:0] a,input [7:0] b,output reg [7:0] out,output reg result_is_zero); //?always @(*) begincase (do_sub)0: out = a+b;1: out = a-b;endcase?if (~out)result_is_zero = 1;end?endmodule??

我的修正（四）

// synthesis verilog_input_version verilog_2001module top_module ( input do_sub,input [7:0] a,input [7:0] b,output reg [7:0] out,output reg result_is_zero); //?always @(*) begincase (do_sub)0: out = a+b;1: out = a-b;endcase?if (out)result_is_zero=0;else result_is_zero=1;end?endmodule?

题目五（Case）该组合电路应该能够识别键0到9的8位键盘扫描代码。它应该指示是否识别出10种情况之一（有效），如果识别出，则检测到了哪个键。修复错误。

module top_module (input [7:0] code,output reg [3:0] out,output reg valid=1 ); //?always @(*)case (code)8'h45: out = 0;8'h16: out = 1;8'h1e: out = 2;8'd26: out = 3;8'h25: out = 4;8'h2e: out = 5;8'h36: out = 6;8'h3d: out = 7;8'h3e: out = 8;6'h46: out = 9;default: valid = 0;endcase?endmodule???

我的修正（五）

module top_module (input [7:0] code,output reg [3:0] out,output reg valid);?// A combinational always block.always @(*) beginout = 0; // To avoid latches, give the outputs a default assignmentvalid = 1; //then override them in the case statement. This is less//code than assigning a value to every variable for every case.case (code)8'h45: out = 0;8'h16: out = 1;8'h1e: out = 2;8'h26: out = 3; // 8'd26 is 8'h1a8'h25: out = 4;8'h2e: out = 5;8'h36: out = 6;8'h3d: out = 7;8'h3e: out = 8;8'h46: out = 9;default: valid = 0;endcaseendendmodule?