若计数器的输入脉冲的频率为f,则输出的Q0、Q1、Q2和Q3端输出脉冲的频率依次为1/2f,1/4f,1/8f/1/16f。
Verilog 代码实现
预分频器代码 prescaler.v
module prescaler(
outputscaler16_o,
outputscaler8_o,
outputscaler4_o,
outputscaler2_o,
inputclk,
inputrstn,
inputen_i
);
reg[3:0]cnt;
reg[3:0]cnt_next;
always@(posedge clk, negedge rstn)
begin
if(!rstn)
cnt <= 4'b0;
else
cnt <= cnt_next;
endalways@(*)
begin
if(en_i)
if(cnt == 4'b1111)
cnt_next = 4'b0;
else
cnt_next = cnt + 1'b1;
else
cnt_next = cnt;
endassign scaler16_o = cnt[3];
assign scaler8_o= cnt[2];
assign scaler4_o= cnt[1];
assign scaler2_o= cnt[0];
endmoduletestbench prescaler_tb.v
module prescaler_tb;
regclk;
regrstn;
regen_i;
wirescaler2_o;
wirescaler4_o;
wirescaler8_o;
wirescaler16_o;
initial
begin
clk= 0;
rstn= 1;
#30rstn = 0;
#100 rstn = 1;
en_i = 1;
repeat(100) @(posedge clk);
$finish;
endalways #20 clk = ~clk;
initial begin
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars();
endprescaleru_prescaler(
.scaler16_o(scaler16_o),
.scaler8_o(scaler8_o),
.scaler4_o(scaler4_o),
.scaler2_o(scaler2_o),
.clk(clk),
.rstn(rstn),
.en_i(en_i)
);
endmodule仿真结果
文章图片
参考资料 【预分频之一】[1] 数字电子技术基础(第五版) 阎石主编
转载于:https://www.cnblogs.com/OneFri/p/6014296.html
