Verilog刷题-2-Build a circuit with no inputs and one output. That output should always drive 1 Verilog刷题

代码

module top_module( output one ); // Insert your code here assign one = 1'b1; endmodule

结果
【Verilog刷题-2-Build a circuit with no inputs and one output. That output should always drive 1】

文章图片

文章图片

这里的warning没啥问题，因为就是题目的要求。

Verilog刷题-2-Build a circuit with no inputs and one output. That output should always drive 1