Verilog刷题-17-Vector3
题目描述
- 文字描述
Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits: - 图示
文章图片
module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );
//assign {w,x,y,z} = {a,b,c,d,e,f,2'b11};
endmodule
结果
文章图片
文章图片
题目网址
【Verilog刷题-17-Vector3】https://hdlbits.01xz.net/wiki/Vector3
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