HDLBits记录（一）
记录在HDLBits上做的题目,如有错误，欢迎指正。
HDLBits记录(一): 1 Getting Started and 2 Verilog Language.
HDLBits记录(二): 3 Circuits / 3.1 Combinational Logic.
HDLBits记录(三): 3 Circuits / 3.2 Sequential Logic.
目录
- 1 Getting Started
- 1.1 Getting Started (Ouput one)
- 1.2 Ouput zero
- 2 Verilog Language
- 2.1 Basic
- 2.2 Vectors
- 2.3 Modules: Hierarchy
- 2.4 Procedures
- 2.5 More Verilog Features
1 Getting Started 1.1 Getting Started (Ouput one)
module top_module( output one );
assign one = 1'b1;
endmodule
1.2 Ouput zero
module top_module( output zero);
assign zero = 1'b0;
endmodule
2 Verilog Language 2.1 Basic
2.1.1 Simple wire
module top_module( input in, output out );
assign out = in;
endmodule
2.1.2 Four wires
module top_module(
input a,b,c,
output w,x,y,z );
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
2.1.3 Inverter
module top_module( input in, output out );
assign out = ~in;
endmodule
2.1.4 AND gate
module top_module(
input a,
input b,
output out );
assign out = a & b;
endmodule
2.1.5 NOR gate
module top_module(
input a,
input b,
output out );
assign out = ~(a|b);
endmodule
2.1.6 XNOR gate
module top_module(
input a,
input b,
output out );
assign out = (a & b) + (!a & !b);
endmodule
2.1.7 Declaring wires
`default_nettype none
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n);
wire one,two;
assign one = a & b;
assign two = c & d;
assign out = one | two;
assign out_n = ~out;
endmodule
2.1.8 7458 chip
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f);
assign p2y = (p2a & p2b ) | (p2c & p2d);
endmodule
2.2 Vectors
2.2.1 Vectors
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0);
assign outv = vec;
assign {o2,o1,o0} = vec;
endmodule
2.2.2 Vectors in more detail
`default_nettype none// Disable implicit nets. Reduces some types of bugs.
module top_module(
input wire [15:0] in,
output wire [7:0] out_hi,
output wire [7:0] out_lo );
assign out_hi = in[15:8];
assign out_lo = in[7:0];
endmodule
2.2.3 Vector part select
module top_module(
input [31:0] in,
output [31:0] out );
assign out[31:24] = in[7:0];
assign out[23:16] = in[15:8];
assign out[15:8] = in[23:16];
assign out[7:0] = in[31:24];
endmodule
2.2.4 Bitwise operators
module top_module(
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_no );
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not[5:3] = ~b;
assign out_not[2:0] = ~a;
endmodule
2.2.5 Four-input gates
module top_module(
input [3:0] in,
output out_and,
output out_or,
output out_xor );
assign out_and = in[3] & in[2] & in[1] & in[0];
assign out_or= in[3] | in[2] | in[1] | in[0];
assign out_xor = in[3] ^ in[2] ^ in[1] ^ in[0];
endmodule
2.2.6 Vector concatenation operator
module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );
assign w = {a, b[4:2] };
assign x = {b[1:0], c, d[4] };
assign y = {d[3:0], e[4:1] };
assign z = {e[0], f, 2'b11};
endmodule
2.2.7 Vector reversal 1
module top_module(
input [7:0] in,
output [7:0] out
);
assign {out[7], out[6], out[5], out[4], out[3], out[2], out[1], out[0] } = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule
2.2.8 Replication operator
module top_module (
input [7:0] in,
output [31:0] out );
assign out = { {24{in[7]}} , in };
endmodule
2.2.9 More replication
module top_module (
input a, b, c, d, e,
output [24:0] out );
//// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}} ,{5{e}} } ^ { 5{a, b, c, d, e} };
endmodule
2.3 Modules: Hierarchy
2.3.1 Modules
module top_module ( input a, input b, output out );
mod_a test (.in1(a), .in2(b), .out(out));
endmodule
2.3.2 connecting ports by position
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a test(out1, out2, a, b, c, d);
endmodule
2.3.3 connecting ports by name
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a test (.in1(a), .in2(b), .in3(c), .in4(d), .out1(out1), .out2(out2));
endmodule
2.3.4 three modules
module top_module ( input clk, input d, output q );
wire q_1, q_2;
my_dff my_dff_1(.clk(clk), .d(d),.q(q_1));
my_dff my_dff_2(.clk(clk), .d(q_1), .q(q_2));
my_dff my_dff_3(.clk(clk), .d(q_2), .q(q));
endmodule
2.3.5 modules and vectors
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output [7:0] q );
wire [7:0] q_1, q_2, q_3;
reg[7:0] q_out_reg;
my_dff8 my_dff8_1(.clk(clk), .d(d),.q(q_1));
my_dff8 my_dff8_2(.clk(clk), .d(q_1), .q(q_2));
my_dff8 my_dff8_3(.clk(clk), .d(q_2), .q(q_3));
always @(*) begin
case (sel)
2'd0: q_out_reg = d;
2'd1: q_out_reg = q_1;
2'd2: q_out_reg = q_2;
2'd3: q_out_reg = q_3;
endcase
endassign q = q_out_reg;
endmodule
2.3.6 adder1
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum);
wire cout;
add16 add16_1(.a(a[15:0]), .b(b[15:0]), .cin(1'b0), .sum(sum[15:0]), .cout(cout));
add16 add16_2(.a(a[31:16]), .b(b[31:16]), .cin(cout), .sum(sum[31:16]), .cout());
endmodule
2.3.7 adder2
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum);
wire cout_1;
add16 add16_1(.a(a[15:0]),.b(b[15:0]),.cin(1'b0),.sum(sum[15:0]),.cout(cout_1));
add16 add16_2(.a(a[31:16]), .b(b[31:16]), .cin(cout_1), .sum(sum[31:16]), .cout());
endmodulemodule add1 ( input a, input b, input cin,output sum, output cout );
assign {cout, sum} = a + b + cin;
endmodule
2.3.8 carry-select adder
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cout;
wire [15:0] sum_1,sum_2;
add16 add16_1(.a(a[15:0]), .b(b[15:0]), .cin(1'b0), .sum(sum[15:0]), .cout(cout));
add16 add16_2(.a(a[31:16]), .b(b[31:16]), .cin(1'b0), .sum(sum_1), .cout());
add16 add16_3(.a(a[31:16]), .b(b[31:16]), .cin(1'b1), .sum(sum_2), .cout());
assign sum[31:16] = cout ? sum_2 : sum_1;
endmodule
2.3.9 adder-subtractor
module top_module(
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire cout;
wire [31:0] b_1;
assign b_1 = b ^ {32{sub}};
add16 add16_1(.a(a[15:0]), .b(b_1[15:0]), .cin(sub), .sum(sum[15:0]), .cout(cout));
add16 add16_2(.a(a[31:16]), .b(b_1[31:16]), .cin(cout), .sum(sum[31:16]), .cout());
endmodule
2.4 Procedures
2.4.1 always blocks 1
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
output wire out_assign,
output reg out_alwaysbloc);
assign out_assign = a & b;
always @(*) begin
out_alwaysblock = a & b;
endendmodule
【HDLBits记录（一）】2.4.2 always blocks 2
// synthesis verilog_input_version verilog_2001
module top_module(
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff);
assign out_assign = a ^ b;
always @(*) begin
out_always_comb = a ^ b;
endalways @(posedge clk) begin
out_always_ff <= a ^ b;
endendmodule
2.4.3 if statement
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always);
assign out_assign = (sel_b1 & sel_b2) ? b : a;
always @(*)begin
if(sel_b1 & sel_b2)
out_always = b;
else
out_always = a;
end
endmodule
2.4.3 if statement latches
// synthesis verilog_input_version verilog_2001
module top_module (
inputcpu_overheated,
output reg shut_off_computer,
inputarrived,
inputgas_tank_empty,
output reg keep_driving);
//always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
else
shut_off_computer = 0;
endalways @(*) begin
if (~arrived)
keep_driving = ~gas_tank_empty;
else
keep_driving = ~arrived;
endendmodule
2.4.4 case statement
// synthesis verilog_input_version verilog_2001
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out);
//always@(*) begin// This is a combinational circuit
case(sel)
3'd0: out = data0;
3'd1: out = data1;
3'd2: out = data2;
3'd3: out = data3;
3'd4: out = data4;
3'd5: out = data5;
default: out = 4'd0;
endcase
endendmodule
2.4.5 priority encoder
// synthesis verilog_input_version verilog_2001
module top_module (
input [3:0] in,
output reg [1:0] pos);
always @(*) begin
case (in)
4'b0000: pos = 2'd0;
4'b0001: pos = 2'd0;
4'b0010: pos = 2'd1;
4'b0011: pos = 2'd0;
4'b0100: pos = 2'd2;
4'b0101: pos = 2'd0;
4'b0110: pos = 2'd1;
4'b0111: pos = 2'd0;
4'b1000: pos = 2'd3;
4'b1001: pos = 2'd0;
4'b1010: pos = 2'd1;
4'b1011: pos = 2'd0;
4'b1100: pos = 2'd2;
4'b1101: pos = 2'd0;
4'b1110: pos = 2'd1;
4'b1111: pos = 2'd0;
default: pos = 2'd0;
endcase
endendmodule
2.4.6 priority encoder with casez
// synthesis verilog_input_version verilog_2001
module top_module (
input [7:0] in,
output reg [2:0] pos);
always @(*)begin
casez (in[7:0])
8'bzzzzzzz1: pos = 3'd0;
8'bzzzzzz1z: pos = 3'd1;
8'bzzzzz1zz: pos = 3'd2;
8'bzzzz1zzz: pos = 3'd3;
8'bzzz1zzzz: pos = 3'd4;
8'bzz1zzzzz: pos = 3'd5;
8'bz1zzzzzz: pos = 3'd6;
8'b1zzzzzzz: pos = 3'd7;
default: pos = 3'd0;
endcase
end
endmodule
2.4.7 avoiding latches
// synthesis verilog_input_version verilog_2001
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up);
always @(*) begin
case (scancode)
16'he06b: begin left = 1;
down = 0;
right = 0;
up = 0;
end
16'he072: begin left = 0;
down = 1;
right = 0;
up = 0;
end
16'he074: begin left = 0;
down = 0;
right = 1;
up = 0;
end
16'he075: begin left = 0;
down = 0;
right = 0;
up = 1;
end
default: beginleft = 0;
down = 0;
right = 0;
up = 0;
end
endcase
end
endmodule
2.5 More Verilog Features
2.5.1 conditional ternary operator
module top_module (
input [7:0] a, b, c, d,
output [7:0] min);
wire [7:0] min_1, min_2;
assign min_1 = (a < b) ? a : b;
assign min_2 = (c < d) ? c : d;
assign min= (min_1 < min_2) ? min_1 : min_2;
endmodule
2.5.2 reduction operators
module top_module (
input [7:0] in,
output parity);
assign parity = ^in;
endmodule
2.5.3 reduction : even wider gates
module top_module(
input [99:0] in,
output out_and,
output out_or,
output out_xor );
assign out_and = & in;
assign out_or= | in;
assign out_xor = ^ in;
endmodule
2.5.4 combinational for-loop vector reversal 2
module top_module(
input [99:0] in,
output [99:0] out
);
reg [6:0] i = 0;
always @(*) begin
for (i = 0;
i < 100;
i = i + 1)begin
out[i] = in[99 - i];
end
endendmodule
2.5.5 combinational for-loop: 255-bit population count
module top_module(
input [254:0] in,
output [7:0] out );
reg [7:0] i;
always @(*)begin
out = 8'd0;
for(i = 0;
i < 255;
i = i + 1)
if (in[i])
out = out + 1'b1;
else
out = out;
end
endmodule
2.5.6 generate for-loop: 100-bit binary adder 2
2.5.7 generate for-loop: 100-bit digit BCD adder 2
推荐阅读
- 一个人的旅行，三亚
- 一个小故事，我的思考。
- 《真与假的困惑》???|《真与假的困惑》??? ——致良知是一种伟大的力量
- 开学第一天（下）
- 一个人的碎碎念
- 20170612时间和注意力开销记录
- 2018年11月19日|2018年11月19日 星期一 亲子日记第144篇
- 遇到一哭二闹三打滚的孩子，怎么办┃山伯教育
- 第326天
- Y房东的后半生14