HDLBits记录（三）
记录在HDLBits上做的题目,如有错误，欢迎指正。
目录
- 3 Circuits
- 3.2 sequential Logic
- 3.2.1 latches and Flip-Flops
- 3.2.2 counters
- 3.2.3 shift registers
- 3.2.4 More Circuits
- 3.2.5 Finite State Machines
3 Circuits 3.2 sequential Logic
3.2.1 latches and Flip-Flops 1 DFF
module top_module (
input clk,// Clocks are used in sequential circuits
input d,
output reg q );
//
always @(posedge clk) begin
q <= d;
end
endmodule
2 DFF
module top_module (
input clk,
input [7:0] d,
output [7:0] q);
always @(posedge clk) begin
q <= d;
endendmodule
3 DFF with reset
module top_module (
input clk,
input reset,// Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
if(reset)
q <= 0;
else
q <= d;
endendmodule
4 DFF with reset value
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q );
always @(negedge clk) begin
if(reset)
q <= 8'h34;
else
q <= d;
end
endmodule
5 DFF with asynchronous reset
module top_module (
input clk,
input areset,// active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk or posedge areset) begin
if(areset)
q <= 0;
else
q <= d;
end
endmodule6 DFF with byte enable
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk)begin
if(!resetn)
q <= 0;
else begin
if(byteena[1])
q[15:8] <= d[15:8];
else
q[15:8] <= q[15:8];
if(byteena[0])
q[7:0] <= d[7:0];
else
q[7:0] <= q[7:0];
end
end
endmodule
7 D latch
module top_module (
input d,
input ena,
output q);
assign q = ena ? d : q;
endmodule
8 DFF
module top_module (
input clk,
input d,
input ar,// asynchronous reset
output q);
always @(posedge clk or posedge ar)begin
if(ar)
q <= 0;
else
q <= d;
end
endmodule
9 DFF
module top_module (
input clk,
input d,
input r,// synchronous reset
output q);
always @(posedge clk)begin
if(r)
q <= 0;
else
q <= d;
end
endmodule
10 DFF+gate
module top_module (
input clk,
input in,
output out);
always @(posedge clk)begin
out <= in ^ out;
end
endmodule
11 mux and DFF
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q);
always @(posedge clk) begin
if(L)
Q <= r_in;
else
Q <= q_in;
endendmodule
12 mux and DFF
module top_module (
input clk,
input w, R, E, L,
output Q
);
always @(posedge clk) begin
if(L)
Q <= R;
else
if(E)
Q <= w;
else
Q <= Q;
end
endmodule
13 DFFs and gate
module top_module (
input clk,
input x,
output z
);
reg [2:0] q = 3'b0;
always @(posedge clk)begin
q[0] <= x ^ q[0];
q[1] <= x & ~q[1];
q[2] <= x | ~q[2];
endassign z = ~(q[0] | q[1] | q[2]);
endmodule
14 creat circuit from truth table (JK)
module top_module (
input clk,
input j,
input k,
output Q);
always @(posedge clk) begin
case({j,k})
2'b00: Q <= Q;
2'b01: Q <= 0;
2'b10: Q <= 1;
2'b11: Q <= ~Q;
endcase
end
endmodule
15 detect an edge
16 detect both edge
17 edge capture register
18 dual-edge triggered flip-flop
module top_module (
input clk,
input d,
output q
);
reg q1,q2;
always @(posedge clk)begin
q1 <= d;
end
always @(negedge clk)begin
q2 <= d;
endassign q = clk ? q1 : q2;
endmodule
3.2.2 counters 【HDLBits记录（三）】1 foub-bit binary counter
module top_module (
input clk,
input reset,// Synchronous active-high reset
output [3:0] q);
always @(posedge clk)begin
if(reset)
q <= 3'b0;
else
q <= q + 1'b1;
endendmodule
2 decade counter
module top_module (
input clk,
input reset,// Synchronous active-high reset
output [3:0] q);
always @(posedge clk)begin
if(reset)
q <= 3'b0;
else
if(q == 4'd9)
q <= 0;
else
q <= q + 1'b1;
end
endmodule
3 decade counter again
module top_module (
input clk,
input reset,
output [3:0] q);
always @(posedge clk)begin
if(reset)
q <= 4'b1;
else
if(q == 4'd10)
q <= 1;
else
q <= q + 1'b1;
endendmodule
4 slow decade counter
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always @(posedge clk)begin
if(reset)
q <= 4'b0;
else
if (slowena)
if(q == 4'd9)
q <= 0;
else
q <= q + 1'b1;
else
q <= q;
end
endmodule
5 counter 1-12
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d);
assign c_enable = enable;
assign c_load = reset | (Q == 4'd12 & enable);
assign c_d = 4'd1;
count4 the_counter (.clk(clk), .enable(c_enable), .load(c_load), .d(c_d), .Q(Q));
endmodule
13 counter 100
14 4- digit decimal counter
module top_module (
input clk,
input reset,// Synchronous active-high reset
output [3:1] ena,
output [15:0] q);
always @(posedge clk) begin
if (reset) begin
ena <= 3'b0;
end
else begin
if (q[3:0] == 4'd8 ) begin
ena[1] <= 1;
end
else
ena[1] <= 0;
if (q[7:4] == 4'd9 && q[3:0] == 4'd8) begin
ena[2] <= 1;
end
else
ena[2] <= 0;
if (q[11:8] == 4'd9 && q[7:4] == 4'd9 && q[3:0] == 4'd8) begin
ena[3] <= 1;
end
else
ena[3] <= 0
end
end always @(posedge clk) begin
if (reset) begin
q <= 16'b0;
end
else begin
if (ena[1]) begin
q[3:0] <= 4'b0;
q[7:4] <= q[7:4] + 1'b1;
end
else begin
q[3:0] <= q[3:0] + 1'b1;
q[7:4] <= q[7:4];
endif (ena[2]) begin
q[7:4] <= 4'b0;
q[11:8] <= q[11:8] + 1'b1;
end
else
q[11:8] <= q[11:8];
if (ena[3]) begin
q[11:8] <= 4'b0;
if (q[15:12] == 4'd9 )
q[15:12] <= 4'b0;
else
q[15:12] <= q[15:12] + 1'b1;
end
else
q[15:12] <= q[15:12];
end
end
endmodule
3.2.3 shift registers 1 4-bit shift registers
module top_module(
input clk,
input areset,// async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
always @(posedge clk or posedge areset) begin
if (areset) begin
q <= 4'b0;
end
else begin
if (load) begin
q <= data;
end
else if (ena) begin
q <= q >> 1;
end
else
q <= q;
end
end
endmodule
2 left/rignt rotator
module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
integer i;
always @(posedge clk) begin
if (load) begin
q <= data;
end
else if (ena == 2'b01) begin
q[99] <= q[0];
for (i = 0;
i <= 98;
i = i + 1)
q[i] <= q[i+1];
end
else if (ena == 2'b10) begin
q[0] <= q[99];
for (i = 1;
i <= 99;
i = i + 1)
q[i] <= q[i-1];
end
else
q <= q;
end
endmodule
3 left/rignt arthmetic shift by 1 or 8
module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk) begin
if (load) begin
q <= data;
end
else if (ena) begin
case (amount)
2'b00: q <= q <<< 1;
2'b01: q <= q <<< 8;
2'b10: q <= {{q[63]},{q[63:1]}};
2'b11: q <= {{8{q[63]}},{q[63:8]}};
endcase
end
else
q <= q;
end
endmodule
4 5-bit LFSR
module top_module(
input clk,
input reset,// Active-high synchronous reset to 5'h1
output [4:0] q
);
always @ (posedge clk) begin
if (reset) begin
q <= 4'b1;
end
else begin
q[4] <= q[0] ^ 1'b0;
q[3] <= q[4];
q[2] <= q[3] ^ q[0];
q[1] <= q[2];
q[0] <= q[1];
end
end
endmodule
5 3-bit LFSR
module top_module (
input [2:0] SW,// R
input [1:0] KEY,// L and clk
output [2:0] LEDR);
// Q
always @(posedge KEY[0]) begin
LEDR[0] <= KEY[1] ? SW[0] : LEDR[2];
LEDR[1] <= KEY[1] ? SW[1] : LEDR[0];
LEDR[2] <= KEY[1] ? SW[2] : (LEDR[1] ^ LEDR[2]);
endendmodule6 32-bit LFSR
module top_module(
input clk,
input reset,// Active-high synchronous reset to 32'h1
output [31:0] q );
always @ (posedge clk) begin
if(reset)
q <= 32'h1;
else begin
q <= {q[0], q[31:1]};
q[31] <= q[0] ^ 1'b0;
q[21] <= q[0] ^ q[22];
q[1]<= q[0] ^ q[2];
q[0]<= q[0] ^ q[1];
end
end
endmodule7 shift register
module top_module (
input clk,
input resetn,// synchronous reset
input in,
output out);
reg q_0,q_1,q_2;
always @(posedge clk) begin
if (!resetn) begin
q_0 <= 0;
q_1 <= 0;
q_2 <= 0;
out <= 0;
end
else begin
q_0 <= in;
q_1 <= q_0;
q_2 <= q_1;
out <= q_2;
end
end
endmodule8 shift register
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
);
//
MUXDFF u_1(.clk(KEY[0]), .w(KEY[3]), .E(KEY[1]), .R(SW[3]), .L(KEY[2]), .q(LEDR[3]));
MUXDFF u_2(.clk(KEY[0]), .w(LEDR[3]), .E(KEY[1]), .R(SW[2]), .L(KEY[2]), .q(LEDR[2]));
MUXDFF u_3(.clk(KEY[0]), .w(LEDR[2]), .E(KEY[1]), .R(SW[1]), .L(KEY[2]), .q(LEDR[1]));
MUXDFF u_4(.clk(KEY[0]), .w(LEDR[1]), .E(KEY[1]), .R(SW[0]), .L(KEY[2]), .q(LEDR[0]));
endmodulemodule MUXDFF (
input clk,
input w,
input E,
input R,
input L,
output q
);
always @(posedge clk) begin
q <= L ? R : (E ? w : q);
end
endmodule9 3-input LUT
module top_module (
input clk,
input enable,
input S,
input A, B, C,
output Z );
reg [7:0] q;
always @(posedge clk) begin
if (enable) begin
q <= q{q[6:0], S};
end
else
q <= q;
end always @(*) begin
case ({A,B,C})
3'b000: Z <= q[0];
3'b001: Z <= q[1];
3'b010: Z <= q[2];
3'b011: Z <= q[3];
3'b100: Z <= q[4];
3'b101: Z <= q[5];
3'b110: Z <= q[6];
3'b111: Z <= q[7];
endcase
end
endmodule3.2.4 More Circuits 3.2.5 Finite State Machines 1 simple FSM 1
module top_module(
input clk,
input areset,// Asynchronous reset to state B
input in,
output out);
//parameter A=1'b0, B=1'b1;
reg state, next_state;
always @(*) begin// This is a combinational always block
// State transition logic
if (state == B)
next_state = in ? B : A;
else if(state == A)
next_state = in ? A : B;
else
next_state = next_state;
endalways @(posedge clk, posedge areset) begin// This is a sequential always block
// State flip-flops with asynchronous reset
if (areset) begin
state <= B;
end
else begin
state <= next_state;
end
end// Output logic
assign out = (state == B);
endmodule2 simple FSM 1.2
module top_module(clk, reset, in, out);
input clk;
input reset;
// Synchronous reset to state B
input in;
output out;
//
reg out;
// Fill in state name declarations
parameter A=1'b0, B=1'b1;
reg present_state, next_state;
always @(posedge clk) begin
if (reset) begin
present_state = B;
end
else begin
case (present_state)
B : if (in == 1'b0)
next_state = A;
else
next_state = present_state;
A : if (in == 1'b0)
next_state = B;
else
next_state = present_state;
endcase// State flip-flops
present_state = next_state;
end
case (present_state)
// Fill in output logic
B : out = 1;
A : out = 0;
endcaseendendmodulesimple FSM 2
推荐阅读
- 放屁有这三个特征的，请注意啦！这说明你的身体毒素太多
- 一个人的旅行，三亚
- 2018-02-06第三天|2018-02-06第三天 不能再了，反思到位就差改变
- 第三节|第三节 快乐和幸福（12）
- android第三方框架（五）ButterKnife
- 20170612时间和注意力开销记录
- 遇到一哭二闹三打滚的孩子，怎么办┃山伯教育
- 三十年后的广场舞大爷
- 一百二十三夜，请嫁给我
- 2018年9月5日，星期三，天气晴