HDLbits答案更新系列19(3.3|HDLbits答案更新系列19(3.3 Building Larger Circuits 3.3.1 Counter with period 1000等)

目录
前言
3.3 Building Larger Circuits
【HDLbits答案更新系列19(3.3|HDLbits答案更新系列19(3.3 Building Larger Circuits 3.3.1 Counter with period 1000等)】3.3.1 Counter with period 1000(Exams/review2015 count1k)
3.3.2 4-bit shift register and down counter(Exams/review2015 shiftcount)
3.3.3 FSM:Sequence 1101 recognizer(Exams/review2015 fsmseq)
结语
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前言 今天我们进入到新的一节,之前的计数器和状态机小节已经搞定了,这一节我们将会用这些基础模块搭建更大的系统,下面我们就开始吧。
3.3 Building Larger Circuits 3.3.1 Counter with period 1000(Exams/review2015 count1k) HDLbits答案更新系列19(3.3|HDLbits答案更新系列19(3.3 Building Larger Circuits 3.3.1 Counter with period 1000等)
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module top_module ( input clk, input reset, output [9:0] q); always@(posedge clk)begin if(reset == 1'b1)begin q <= 10'd0; end else if(q == 10'd999)begin q <= 10'd0; end else begin q <= q + 1'b1; end endendmodule

这道题是一个计数周期为1000的计数器,只需在计数到999的时候清零即可,没有难度。
3.3.2 4-bit shift register and down counter(Exams/review2015 shiftcount) HDLbits答案更新系列19(3.3|HDLbits答案更新系列19(3.3 Building Larger Circuits 3.3.1 Counter with period 1000等)
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module top_module ( input clk, input shift_ena, input count_ena, input data, output [3:0] q); always@(posedge clk)begin case({shift_ena, count_ena}) 2'b10:begin q <= {q[2:0], data}; end 2'b01:begin q <= q - 1'b1; end endcase end/* //second way always@(posedge clk)begin if(shift_ena)begin q <= {q[2:0], data}; end else if(count_ena)begin q <= q - 1'b1; end end */endmodule

题目说实现一个4bit移位寄存器,该寄存器还可以做递减计数器,当shift_ena有效时,数据开始循环移位,当count_ena为1时,该移位寄存器做递减器。题目特意说明这两个信号不会同时为1,博主给出两种方法,大家看一看就好。
3.3.3 FSM:Sequence 1101 recognizer(Exams/review2015 fsmseq) HDLbits答案更新系列19(3.3|HDLbits答案更新系列19(3.3 Building Larger Circuits 3.3.1 Counter with period 1000等)
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module top_module ( input clk, input reset,// Synchronous reset input data, output start_shifting); parameter S0 = 3'd0, S1 = 3'd1, S2 = 3'd2, S3 = 3'd3, S4 = 3'd4; reg [2:0] current_state; reg [2:0] next_state; always@(posedge clk)begin if(reset)begin current_state <= S0; end else begin current_state <= next_state; end endalways@(*)begin case(current_state) S0:begin next_state = data ? S1 : S0; end S1:begin next_state = data ? S2 : S0; end S2:begin next_state = data ? S2 : S3; end S3:begin next_state = data ? S4 : S0; end S4:begin next_state = S4; end default:begin next_state = S0; end endcase endalways@(posedge clk)begin if(reset)begin start_shifting <= 1'b0; end else if(next_state == S4)begin start_shifting <= 1'b1; end end//assign start_shifting = current_state == S4; endmodule

超级经典的序列检测,大家一定要多多练习,简直是笔试经典题目了。
结语 今天更新这三道题目吧,第三道尤其要注意,真的是太经典了,各种面试笔试题中都会出现,大家一定要认真去做一做。如果有哪里代码有问题,欢迎随时指出哦~
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