HDLBits Day12 count clock 做一个钟表 Verilog

【HDLBits Day12 count clock 做一个钟表】
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1.BCD码进位时，判断条件是 if(m < 8’h59)，这里是用16进制数表示，即4位二进制数表示5，四位二进制数表示9，BCD数实际上就是十六进制数，不过是人为设置满10进1.
自己写的：

module top_module( input clk, input reset, input ena, output pm, output [7:0] hh, output [7:0] mm, output [7:0] ss); always@(posedge clk ) if (reset) ss <= 8'h00; else if(ena) begin if(ss == 8'h59) ss <= 8'h00; elsebegin if(ss[3:0] < 4'h9) ss[3:0] <= ss[3:0] + 1'h1; else begin ss[3:0] <= 0; ss[7:4] <= ss[7:4] + 1'h1; end end end always@(posedge clk) if (reset) mm <= 8'h00; else if(ena) begin if(ss == 8'h59) if(mm == 8'h59) mm <= 8'h00; else if(mm[3:0] < 4'h9) begin mm[3:0] <= mm[3:0] + 1'h1; end else begin mm[3:0] <= 0; mm[7:4] <= mm[7:4] + 1'h1; end endalways@(posedge clk ) if (reset) hh <= 8'h12; else if(ena) begin if(mm == 8'h59 && ss == 8'h59) begin if(hh == 8'h12) hh <= 8'h01; else if(hh[3:0] < 4'h9) begin hh[3:0] <= hh[3:0] + 1'h1; end else begin hh[3:0] <= 0; hh[7:4] <= hh[7:4] + 1'h1; end endend always@(posedge clk ) if (reset) pm <= 0; else if(hh ==8'h11 && mm == 8'h59 && ss == 8'h59) pm =!pm; endmodule

时分秒分开写的，以为这样理解起来简单。至于为什么用同步复位，异步复位时序不对，同步复位时序对了，就这样，题面里没有说明白，答案是这样。
人家写的：

module top_module ( input clk, input reset, input ena, output pm, output [7:0] hh, output [7:0] mm, output [7:0] ss ); reg p; //0 was am, 1 was pm reg [7:0] h; reg [7:0] m; reg [7:0] s; always @ (posedge clk) begin if(reset) begin p <= 0; h <= 8'h12; m <= 8'h00; s <= 8'h00; end else begin if(ena) begin if(s < 8'h59) begin if(s[3:0] < 4'h9) begin s[3:0] <= s[3:0] + 1'h1; end else begin s[3:0] <= 0; s[7:4] <= s[7:4] + 1'h1; end end else begin s <= 0; if(m < 8'h59) begin if(m[3:0] < 4'h9) begin m[3:0] <= m[3:0] + 1'h1; end else begin m[3:0] <= 0; m[7:4] <= m[7:4] + 1'h1; end end else begin m <= 1'h0; if(h == 8'h11) p = !p; if(h < 8'h12) begin if(h[3:0] < 4'h9) h[3:0] <= h[3:0] + 1'h1; else begin h[3:0] <= 4'h0; h[7:4] <= h[7:4] + 1'h1; end end else begin h <= 1'h1; end end end end end endassign pm = p; assign hh = h; assign mm = m; assign ss = s; endmodule

tb文件：

`timescale 1ns / 1ns module tb(); reg clk,reset,ena; wire pm; wire[7:0] hh,mm,ss; syn_fifo syn_fifo ( clk, reset, ena, pm, hh, mm, ss ); initial begin clk = 1'b0; forever #10 clk = ~clk; end initial begin reset = 1'b0; ena = 1'b1; #100 reset = 1'b1; #100 reset = 1'b0; end endmodule