Fsm1_hdlbits
【Fsm1_hdlbits】状态机学习link：
https://wenku.baidu.com/view/9e44f7650066f5335a8121e3.html
module top_module(
input clk,
input areset,// Asynchronous reset to state B
input in,
output out);
//parameter A=0, B=1;
reg state, next_state;
always @(*) begin// This is a combinational always block
// State transition logic
case (state)
A: next_state = in? A:B;
B: next_state = in? B:A;
endcase
endalways @(posedge clk, posedge areset) begin// This is a sequential always block
// State flip-flops with asynchronous reset
if (areset)
state <= B;
else
state <= next_state;
end// Output logic
// assign out = (state == ...);
assign out = (state == B);
endmodule
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