【HDLbits|Circuits--Sequential Logic--Latches and Flip-Flops--Exams/2014 q4a】网址:https://hdlbits.01xz.net/wiki/Exams/2014_q4a
module top_module (
input clk,
input w, R, E, L,
output Q
);
wire temp1, temp2;
assign temp1 = E ? w:Q;
assign temp2 = L ? R:temp1;
//与上题类似,不做赘述always @ (posedge clk)
begin
Q <= temp2;
endendmodule
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