verilog|verilog实现1101序列检测器 verilog|verilog

第一种使用摩尔型有限状态机

`timescale 1ns / 1ps module sequence( input in, input clk, input reset, output check ); //同步置位---reset //实现1101序列的检测器//定义状态 parameter idle=0, bit1=1, bit2 =2, bit3=3, bit4=4; reg [2:0] state, next_state; //组合逻辑实现转态的转变 always @(*) begin case(state) idle: next_state = in ? bit1 : idle; bit1: next_state = in ? bit2 : idle; bit2: next_state = in ? bit2 : bit3; bit3: next_state = in ? bit4 : idle; bit4: next_state = in ? bit2 : idle; default: next_state = idle; endcase end//时序逻辑 always @(posedge clk) begin if(reset) state <= idle; else state <= next_state; end//组合逻辑输出 assign check = (state == bit4); endmodule

test_bench为：

`timescale 1ns / 1ps module tb_sequence; reg clk; reg reset; wire check; reg in; //时钟设计 initial begin clk = 1'b0; end always begin #10; clk = ~clk; end //reset信号 initial begin reset = 1'b0; #5; reset = 1'b1; #10; reset <= 1'b0; end //in信号 initial begin in = 1'b0; #20; in = 1'b1; #40; in = 1'b0; #20; in = 1'b1; #40; in = 1'b0; #20; in = 1'b1; endsequence u1( .clk(clk), .in(in), .reset(reset), .check(check) ); endmodule

【verilog|verilog实现1101序列检测器】仿真的波形图