Fsm_serialdata_hdlbits
【Fsm_serialdata_hdlbits】https://hdlbits.01xz.net/wiki/Fsm_serialdata
文章图片
看图发现先进的是bit0
module top_module(
input clk,
input in,
input reset,// Synchronous reset
output [7:0] out_byte,
output done
);
//
reg [9:0] d;
// Use FSM from Fsm_serial
parameter stop = 0,b0=1,b1=2,b2=3,b3=4,b4=5,b5=6,b6=7,b7=8,stop_ok=9,stop_notok=10,start = 11;
//parameter idle = 0,start = 1,b0=2,b1=3,b2,=4,b3,b4,b5,b6,b7,stop;
reg [4:0]state ,next;
always @(*)
begin
case(state)
stop:next = (~in)? start:stop;
start: next = b0;
b0: next =b1;
b1: next = b2;
b2: next = b3;
b3: next = b4;
b4: next = b5;
b5: next = b6;
b6: next = b7;
b7: next = in?stop_ok:stop_notok;
//stop: next = in?stop_ok: idle;
stop_ok: next = (~in)?start:stop;
stop_notok: next = in?stop:stop_notok;
endcase
endalways @(posedge clk)
begin
if (reset)
begin
state <= stop;
d<=9'b0;
end
else
begin
state <= next;
d<= {in,d[9:1]};
endendassign done =(state ==stop_ok);
assign out_byte = d[8:1];
// New: Datapath to latch input bits.endmodule推荐阅读
- STM32F1 FSMC 初步理解1
- 如何使用MM32F3270单片机FSMC驱动外部NOR Flash
- Finite State Machines (FSM)
- HDLBits Day12 count clock 做一个钟表
- HDLbits答案更新系列23（5|HDLbits答案更新系列23（5 Verification: Reading Simulation）
- HDLbits答案更新系列19（3.3|HDLbits答案更新系列19（3.3 Building Larger Circuits 3.3.1 Counter with period 1000等）
- HDLbits答案更新系列10（3.2|HDLbits答案更新系列10（3.2 Sequential Logic 3.2.4 More Circuits）
- HDLbits答案更新系列13（3.2.5|HDLbits答案更新系列13（3.2.5 Finite State Machines 3.2.5.10 Lemmings 1等）
- HDLbits答案更新系列9（3.2|HDLbits答案更新系列9（3.2 Sequential Logic 3.2.3 Shift Registers）
- HDLbits答案更新系列8（3.2|HDLbits答案更新系列8（3.2 Sequential Logic 3.2.2 Counters）