HDLbits|Circuits--Sequential Logic--Latches and Flip-Flops--Dualedge

【HDLbits|Circuits--Sequential Logic--Latches and Flip-Flops--Dualedge】网址:https://hdlbits.01xz.net/wiki/Dualedge
第一种解法:

module top_module ( input clk, input d, output q ); regm = 1'b0; regn = 1'b0; always@(posedge clk) begin m = d; endalways@(negedge clk)

    推荐阅读