【HDLbits|Circuits--Sequential Logic--Latches and Flip-Flops--Dualedge】网址:https://hdlbits.01xz.net/wiki/Dualedge
第一种解法:
module top_module (
input clk,
input d,
output q
);
regm = 1'b0;
regn = 1'b0;
always@(posedge clk)
begin
m = d;
endalways@(negedge clk)
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