【HDLbits|Circuits--Sequential Logic--Latches and Flip-Flops--Edgecapture】网址：https://hdlbits.01xz.net/wiki/Edgecapture
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0] r_in;
always@(posedge clk)
begin
r_in = in;
endalways@(posedge clk)begin
if(reset)begin
out <= 32'd0;
end
else begin
out <= ~in & r_in | out;
end
endendmodule推荐阅读
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