#|HDLBits 系列（31）Serial Receiver and Datapath #|HDLBits

目录
序言
原题复现
我的设计
序言上篇博文：
HDLBits 系列（30）Serial Receiver
写了串行接收器如何接收8位串行数据，正确接收8位串行数据后给一个接收完毕标志信号，这篇博文来继续进一步输出正确接收的串行数据，在done有效时刻输出并行的8bit数据。
特别容易实现，对上篇博客的代码进行略微添加即可。需要注意的是这种uart协议先发送的bit位为低bit位。
原题复现先给出原题，在给出设计：

Now that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don't-care otherwise.
Note that the serial protocol sends the least significant bit first.

#|HDLBits 系列（31）Serial Receiver and Datapath

文章图片

我的设计设计如下：

module top_module( input clk, input in, input reset,// Synchronous reset output [7:0] out_byte, output done ); //// Use FSM from Fsm_serial localparam START = 0, B1 = 1, B2 = 2, B3 = 3, B4 = 4, B5 = 5, B6 = 6, B7 = 7, B8 = 8, STOP = 9, DONE0 = 10, DONE1 = 11; reg [3:0] state, next_state; always@(*) begin case(state) START: begin if(in == 0) next_state = B1; else next_state = START; end B1: begin next_state = B2; end B2: begin next_state = B3; end B3: begin next_state = B4; end B4: begin next_state = B5; end B5: begin next_state = B6; end B6: begin next_state = B7; end B7: begin next_state = B8; end B8: begin next_state = STOP; end STOP: begin if(in == 0) next_state = DONE1; else next_state = DONE0; end DONE0: begin if(in == 1) next_state = START; else next_state = B1; end DONE1: begin if(in == 0) next_state = DONE1; else next_state = START; end default: begin next_state = START; endendcase endalways@(posedge clk) begin if(reset) state <= START; else state <= next_state; endassign done = (state == DONE0) ? 1 : 0; // New: Datapath to latch input bits. reg [7:0] out_byte_mid; always@(*) begin case(state) START: begin ; end B1: begin out_byte_mid[0] = in; end B2: begin out_byte_mid[1] = in; end B3: begin out_byte_mid[2] = in; end B4: begin out_byte_mid[3] = in; end B5: begin out_byte_mid[4] = in; end B6: begin out_byte_mid[5] = in; end B7: begin out_byte_mid[6] = in; end B8: begin out_byte_mid[7] = in; end STOP: begin ; end DONE0: begin ; end DONE1: begin ; end default: begin ; endendcase end assign out_byte = (done == 1)? out_byte_mid:'bz; endmodule

测试成功。
【#|HDLBits 系列（31）Serial Receiver and Datapath】